DEVICES FOR MULTIPLYING MODULO NUMBERS WITH ANALYSIS OF THE LOWER BITS OF THE MULTIPLIER - S. Tynymbayev; R. Sh. Berdibayev; T. Omar; S. A. Gnatyuk; T. A. Namazbayev; S. Adilbekkyzy (Scientific Journal of Pedagogy and Economics, 2019)
Various approaches of modulo multiplying multi-bit (large) numbers in modulus are considered. An algorithm for multiplying numbers is given, where the modular multiplication process is divided into steps, and in each step, by combining the multiplication operations of the previous partial remainder by two with the operation of reducing the multiplication results modulo, partial remainders is formed. The circuit diagrams of multipliers of numbers modulo with the analysis of the lower bits of the multiplier with the sequential and matrix formation of remainders are considered. The proposed modulo multipliers do not require pre-calculations and all calculations do not go beyond the bit grid of the module.